An LCD has the advantages of portability, low power consumption, and low radiation, and has been widely used in various portable information products such as notebooks, personal digital assistants (PDAs), video cameras and the like. Furthermore, the LCD is considered by many to have the potential to completely replace CRT (cathode ray tube) monitors and televisions.
An LCD generally includes a color filter substrate, a TFT array substrate, and a liquid crystal layer sandwiched between the two substrates. When an LCD works, an electric field is applied to liquid crystal molecules in each of selected pixel regions of the liquid crystal layer. In these pixel regions, the liquid crystal molecules change their orientations. Thereby, the liquid crystal layer provides anisotropic transmittance of light therethrough. Thus the amount of the light penetrating the color filter substrate at each of the selected pixel regions is adjusted by controlling the strength of the electric field. In this way, desired pixel colors are obtained at the color filter substrate, and the arrayed combination of the pixel colors provides an image viewed on a display screen of the LCD.
FIG. 13 is a schematic, top plan view showing structure of part of a typical TFT array substrate. The TFT array substrate 10 includes a plurality of gate lines 100 that are parallel to each other and that each extend along a first direction, and a plurality of data lines 110 that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The smallest rectangular area formed by any two adjacent gate lines 100 together with any two adjacent data lines 110 defines a pixel region thereat. In each pixel region, a TFT 130 is provided in the vicinity of a respective point of intersection of one of the gate lines 100 and one of the data lines 110. A pixel electrode 140 is connected to the TFT 130. A capacitor electrode 121 parallel to the gate lines 100 underlies part of the pixel electrode 140 to form a storage capacitor 120.
FIG. 14 is a flowchart summarizing a typical method for manufacturing the TFT array substrate 10. The method mainly includes the following steps, which are for convenience described in relation to a single pixel region only:                step a: forming a gate metal layer and a first photo-resist layer;        step b: forming a gate electrode and a capacitor electrode;        step c: forming an insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, a source/drain metal layer, and a second photo-resist layer in turn;        step d: forming a TFT unit and a storage capacitor;        step e: forming a transparent metallic layer and a third photo-resist layer; and        step f: forming a source electrode, a drain electrode, and a pixel electrode.        
FIG. 15 through FIG. 19 are schematic, side cross-sectional views corresponding to line XV-XV of the TFT array substrate 10 of FIG. 13, with each of FIGS. 15-19 relating to at least one of manufacturing steps of the method of FIG. 14. The manufacturing steps are described in details as follows:
In step 1, referring to FIG. 15, an insulating substrate 11 having a TFT area 12, a display area 13, and a capacitor area 14 is provided. A gate metal layer 101 is deposited on the transparent substrate 11, then a first photo-resist layer 102 is deposited on the gate metal layer 101.
In step 2, referring also to FIG. 16, the first photo-resist layer 102 is exposed using a first photo mask (not shown), and then is developed. Thereby, a first photo-resist pattern is formed. The gate metal layer 101 is etched according to the first photo-resist pattern, thereby forming a gate electrode 132 and a capacitor electrode 121. Thus, the gate electrode 132 positioned at the TFT area 12 and the first capacitor electrode 121 positioned at the capacitor area 14 are formed by a first photolithographic process.
In step 3, referring also to FIG. 17, a gate insulating layer 103, an amorphous silicon layer 104, a doped amorphous silicon layer 105, a source/drain metal layer 106, and a second photo-resist layer 107 are sequentially formed on the insulating substrate 11 having the gate electrode 132 and the first capacitor electrode 121 formed thereon.
In step 4, referring also to FIG. 18, the second photo-resist layer 107 is exposed using a second photo mask (not shown), and then is developed. Thereby, a second photo-resist pattern is formed. The source/drain metal layer 106, the doped amorphous silicon layer 105, the amorphous silicon layer 104, and the gate insulating layer 103 at the display area 13 are etched according to the second photo-resist pattern, thereby forming a TFT unit 130 and a storage capacitor 120. The storage capacitor 120 includes the first capacitor electrode 121, a second capacitor electrode 122, and the doped amorphous silicon layer 105, the amorphous silicon layer 104 and the gate insulating layer 103 sandwiched between the two electrodes 121, 122. The TFT unit 130 includes the gate electrode 132, the gate insulating layer 103, the amorphous silicon layer 104, the doped amorphous silicon layer 105, and the source/drain metal layer 106. Thus, the TFT unit 130 and the storage capacitor 120 are formed by a second photolithographic process which includes step 3 and step 4.
In steps 5 and 6, referring also to FIG. 19, a transparent metallic layer (not shown) and a third photo-resist layer (not shown) are formed on the insulating substrate 11 having the TFT unit 130 and the storage capacitor 120 formed thereon. The transparent metallic layer can for example be made of ITO (Indium-Tin Oxide) or IZO (Indium-Zinc Oxide). The third photo-resist layer is exposed and then is developed, thereby forming a third photo-resist pattern. The transparent metallic layer is etched according to the third photo-resist pattern, thereby forming a pixel electrode 140. The source/drain metal layer 106 is etched, thereby forming a source electrode 131 and a drain electrode 133 of the TFT 130. Furthermore, a portion of the doped amorphous silicon layer 105 below a gap between the source and drain electrodes 131, 133 is etched by a wet etching method. Thereby, a groove 138 is commonly defined in the gap between the source and drain electrodes 131, 133 and the doped amorphous silicon layer 105. Thus, the completed TFT array substrate 10 is finally obtained by a third photolithographic process which includes step 5 and step 6.
A capacitance CST of the storage capacitor 120 can be calculated according to the following formula:
      C    sr    =            ɛ      ·      A        d  In the formula, “∈” represents a dielectric constant of the insulation layers between the first capacitor electrode 121 and the second capacitor electrode 122. “A” represents an area of the first capacitor electrode 121 opposite to the second capacitor electrode 122. “d” represents a distance between the first capacitor electrode 121 and the second capacitor electrode 122, and is equal to a combined thickness of an overlying portion of the gate insulating layer 103, the amorphous silicon layer 104, and the doped amorphous silicon layer 105. According to the above formula, a capacitance of the storage capacitor 120 is proportional to the electrode area “A”, and is inversely proportional to the distance “d”.
In order to improve the display quality of an LCD having the TFT array substrate 10, a capacitance of the storage capacitor 120 needs to be high. However, it is difficult to reduce the distance “d” between the first capacitor electrode 121 and the second capacitor electrode 122 of the storage capacitor 120, because the thickness of the gate insulating layer 103 of the TFT unit 130 must be kept at or above a minimum predetermined threshold thickness. On the other hand, if the electrode area “A” is increased to increase the capacitance of the storage capacitor 120, the aperture ratio of the TFT array substrate 10 is reduced. The reduced aperture ratio may diminish the display quality of the LCD.
What is needed, therefore, is a method for manufacturing a TFT array substrate of an LCD that can overcome the above-described deficiencies. What is also needed is a TFT array substrate made according to the above method.